The present invention relates to a method and an apparatus for wiring the surface of a semiconductor device and also relates to a semiconductor device having wiring formed by the said method and apparatus. In particular, the present invention is concerned with a wiring modifying method and an apparatus suitable for specifying a defective portion present partially in a semiconductor device manufactured for trial, also suitable for specifying a cause of the defect, or repair of the defect, and is further concerned with a semiconductor device.
Semiconductor devices are becoming finer and finer in structure and high in integration for grade-up and speed-up purposes. Accordingly, the development of a semiconductor device more and more difficult, resulting in a longer period required for such development. This situation indicates that the circuit manufacturing technique of "cut and try" is necessary also in the design of LSI. If a semiconductor device, which affords complete operations temporarily, is obtained by specifying a defective portion on a chip which does not fully operate in a conventional design, by cutting the line present in that defective portion, or forming a line in a desired part, or repairing a defective wiring, then the subsequent evaluation of characteristics and alteration of design can be performed rapidly and it becomes possible to deliver such semiconductor devices as technical samples.
As the prior art, for example as described on pages 27 to 32 of "Semiconductor World" November 1987 number, there has been introduced a method in which holes are formed in the surface passivation and an inter-layer insulating film of an LSI chip by the use of a focused ion beam (FIB) to expose wiring portions, then CVD gas is introduced and metallic wiring is formed also by the use of FIB.
Also, there has been introduced a method in which molybdenum wiring is formed on a silicon base coated with SiO.sub.2 using the laser CVD technique, as described in Extended Abstracts of the 17th Conference on Solid State Devices and Materials, Tokyo, (1985), pp. 193-196.
Further known as prior art are U.S. Pat. Nos. 4,868,068; 4,503,329; and 4,609,809, Japanese Patent Laid Open No. 229957/87, and "Extended Abstracts (the 49th Autumn Meeting, 1988) the Japan Society of Applied Physics", (October 1988), p. 534.
According to the above first conventional technique, or by combination of the first conventional technique with the second also referred to above, it is possible to cut unnecessary wiring or form additional wiring, whereby it is possible to repair an LSI chip which does not operate due to defective design or defective process and obtain an LSI chip now capable of operating in a satisfactory manner. However, there still remains the problem that the LSI chip thus obtained is not fully reliable.